module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
	
	localparam IDLE=3'b000;
	localparam S1=3'b001;//1
	localparam S2=3'b010;//11
	localparam S3=3'b011;//110
	localparam S4=3'b100;//1101,shift_ena=1
	localparam S5=3'b101;//1101,counting=1
	localparam S6=3'b110;//1101,done=1
	
	reg [2:0]state;
	reg [2:0]next_state;
	always@(posedge clk)begin
		if(reset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	reg cout_s;
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=(data)?S1:IDLE;
				cout_s=1'b0;
			end
			S1:begin
				next_state=(data)?S2:IDLE;
				cout_s=1'b0;
			end
			S2:begin
				next_state=(data)?S2:S3;
				cout_s=1'b0;
			end
			S3:begin
				next_state=(data)?S4:IDLE;
				cout_s=1'b0;
			end
			S4:begin//shift_ena=1
				next_state=(cout_r>3'b010)?S5:S4;
				cout_s=1'b1;
			end
			S5:begin//counting=1
				next_state=(done_counting)?S6:S5;
				cout_s=1'b0;
			end
			S6:begin//done=1
				next_state=(ack)?IDLE:S6;
				cout_s=1'b0;
			end
		endcase
	end
	assign shift_ena=state==S4;
	assign counting=state==S5;
	assign done=state==S6;
	
	reg[2:0]cout_r;
	always@(posedge clk)begin
		if(reset)begin
			cout_r<=3'b000;
		end
		else begin
			if(cout_s)
			begin
				if(cout_r<3'b100)
					cout_r=cout_r+3'b001;
				else
					cout_r=cout_r;
			end
			else
				cout_r=3'b000;
		end
	end

endmodule